1.
K JL, G S. Area and Speed Efficient FPGA Design of S-Box AES-256 Galois Field Approch Based on Logic. JETIA [Internet]. 28Aug.2024 [cited 18Nov.2024];10(48):105-14. Available from: http://br940.teste.website/~itegamjetia/journal/index.php/jetia/article/view/915